Layout-driven Logic Optimization
نویسندگان
چکیده
With the advent of deep sub-microntechnologies,interconnectloads and delays are becoming dominant. Consequently, the currently used design ow of iterativelyperforming logic synthesis with statistical wire-load models, doing placement & routing, extracting par-asitics, and using them back in the synthesis tool runs into serious timing convergence problems. Layout-driven synthesis has become the need of the day. In this paper, we present a layout-driven optimization methodology that incorporates logic-level transformations for improving the delay and area of a mapped, block-placed, and globally routed design under certain constraints such as area availability , congestion, hold-time, and pin drive, etc. We argue that this is the right stage for optimization. Only those transformations that are local, incremental, and layout-friendly are incorporated. Examples of such transformations are net buuering, gate resizing, generalized DeMorgan transform, and pin permutation. We propose a simple ow to simultaneously improve the delay and area of the design under these constraints. We applied this ow on large, already optimized, industrial designs and obtained signiicant delay and area improvements.
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